Hi Steve,
Always impress with your digging into these
anomalies!
So what are the relevant factors looking at the black
box.
One thing we know is that the interval between
pulses becomes greater as the rpm is lowered. While the peak voltage
probably remains fairly constant - the average voltage will decrease due to the
lower pulse duty cycle. Also based on your analysis, a 1K ohm load on the
input circuit reduces the pulse peak voltage level from approx +13.5 volts to
around +6.00 volts peak - which given the same pulse duty cycle would mean
even a lower average voltage - after which the engine runs OK at
lower rpm.
I suspect the EC has a limiting circuit of some type to
reduce the +13.5 volt peaks to that suitable for input to a microcontroller chip
(generally +5 volts TTY). I use a combination of a zener diode and a
dropping resistor in my EFISM such that any voltage above 5 volts causes the
diode to conduct and clip/limit the peak to around 5 volts. There are, of
course, many other voltage limiting circuit methods with different
characteristics that might be affected differently with a lower peak or average
voltage or the 1K loading.
Analog SWAG:
Interaction of pulse train and a capacitive element
of the EC
IF for example the circuit was such that the pulse train
kept some capacitive element repeatedly trigger so as to be discharged
between pulses with the rpm above a specific rpm, then as the duration
between pulses became longer (with the lower rpm) it might reach a critical
point where the capacitor never becomes completely discharged -I.e
the discharging pulse does not occur frequently enough to bring/keep the
capacitor to zero volt level between pulses - as an example. Adding
the resistor may result in a quicker discharge circuit than
without the resistor- thereby again permitting capacitor to completely discharge
between pulses and the circuit to work at lower rpms . This quicker
discharge and the lower peak voltage may combine to permit the
capacitor to completely discharge at your lower rpm. The lower
voltage seen may only be a side effect and not the reason for the circuit
now working. Just one thought.
Digital SWAG:
I don't see how the 1K resistor would play in this
scenario, but I'm throwing it in for consideration.
One problem I ran into early on with my EFISM
was that the Pulse circuit in the microchip had only a word (16
bits) wide register to store pulse timing data, meaning that no more that
65535 CPU clock tics could be stored. In my case with an 8Mhz clock tic it
mean that any Low rpm with an interval of greater than 122 msec (approx 500 rpm
or lower) would overflow the word memory size - causing errors. If the CPU
clock tic is at a higher rate the minimum rpm is raised and if lower cock tic
rate the min rpm level is lower.
I had to add a flag to signal when the pulse
duration memory register overflowed and then use that flag (when set) to
add 65535 to the pulse interval clock tic count to calculate the correct
rpm, otherwise the rpm calculated was in error.
So again, this is probably not a factor - as I don't see
where the 1K resistor or lower peak voltage would play a role, but thought I
would throw it out for consideration.
All I can think of for the moment
Ed